Novel lateral double diffused metal oxide semiconductor device

ABSTRACT

An embodiment of the instant invention is a transistor formed on a semiconductor substrate of a first conductivity type and having an upper surface, the transistor comprising: a well region (well  204  of FIG.  1   a ) formed in the semiconductor substrate (layer  202  of FIG.  1   a ), the well region of a second conductivity type opposite that of the first conductivity type; a source region (source region  208  of FIG.  1   a ) formed in the well region in the semiconductor substrate, the source region of the second conductivity type; a drain region (drain  210  of FIG.  1   a ) formed in the semiconductor substrate and spaced away from the source region by a channel region (given by length L 1+ L 2 ), the drain region of the second conductivity type; a conductive gate electrode (layer  218  of FIG.  1   a ) disposed over the semiconductor substrate and over the channel region; a gate insulating layer (layer  214  of FIG.  1   a ) disposed between the conductive gate electrode and the semiconductor substrate and having a length, the gate insulating layer comprising: a first portion of the gate insulating layer which has a first length (L 1 ) and a first thickness; a second portion of the gate insulating layer which has a second length (L 2 ) and a second thickness which is substantially thicker than the first thickness, the sum of the first length and the second length equalling the length of the gate insulating layer; and wherein the first portion of the gate insulating layer being situated proximate to the source region and spaced away from the drain region by the second portion of the gate insulating layer; and wherein the well region having a dopant concentration less than that of the source region and the drain region, the well region extends at least from source region towards the drain region so as to completely underlie the first portion of the gate insulating layer and to underlie at least the second portion of the gate insulating layer.

FIELD OF THE INVENTION

[0001] The instant invention pertains to a semiconductor device and morespecifically to a lateral double diffused metal oxide semiconductordevice.

BACKGROUND OF THE INVENTION

[0002] An ever present trend in semiconductor device manufacturinginvolves the reduction in size of devices while trying to reduce thepower consumed by devices during both their “on” state and, moreimportantly, during their “off” state. However, while most devices on acircuit need to quite fast and they can have lower “on” state and “off”state power consumption, some devices which can handle higher powersneed to be provided on the chip. For instance, a processor which needsan output which can run a small motor on a hard-disk drive or aprocessor which has an output that can run the windshield wiper motorson an automobile. The quicker devices, which typically consume lesspower, provide the computational power while the more rugged devices,which typically consume more power, supply the necessary voltage andpower to run the exterior motors. In the past, the output of theprocessor was connected to a series of power devices, which were on adifferent chip, and the power devices would drive the motors. However,it is considerably less expensive and higher performance can be derivedfrom having both the lower power, faster processing devices on the samesubstrate as the higher power, more rugged power devices (commonlyreferred to as intelligent power devices).

[0003] A problem with this technique is that it can be quite difficultto simultaneously fabricate the lower power, faster devices with thehigher power, rugged devices. For instance, the gate dielectric on thelower power devices needs to be quite thin so that threshold voltage ofthe device remains low and the switching speed of the device remainsquite fast, but in order to be able to handle the larger voltages of thehigher power, the higher power devices need a thicker gate dielectric.In addition, power devices typically need a more complex series of dopedregions so as to provide low resistance current paths without riskingthe chance of “latching up”.

[0004] Another problem with the integration of logic devices with thepower devices involves the voltage supplied to each of the devices.Typically, the power devices require higher supply voltages so as toproperly turn the devices on and to run them efficiently. It isdesirable to fabricate a power device which can efficiently supply theappropriate power needed and having a higher breakdown voltage (BV)while having lower on resistance (R_(sp)), lower threshold voltage(V_(T)), and faster switching times.

SUMMARY OF THE INVENTION

[0005] An embodiment of the instant invention is a transistor formed ona semiconductor substrate of a first conductivity type and having anupper surface, the transistor comprising: a well region formed in thesemiconductor substrate, the well region of a second conductivity typeopposite that of the first conductivity type; a source region formed inthe well region in the semiconductor substrate, the source region of thesecond conductivity type; a drain region formed in the semiconductorsubstrate and spaced away from the source region by a channel region,the drain region of the second conductivity type; a conductive gateelectrode disposed over the semiconductor substrate and over the channelregion; a gate insulating layer disposed between the conductive gateelectrode and the semiconductor substrate and having a length, the gateinsulating layer comprising: a first portion of the gate insulatinglayer which has a first length and a first thickness; a second portionof the gate insulating layer which has a second length and a secondthickness which is substantially thicker than the first thickness, thesum of the first length and the second length equalling the length ofthe gate insulating layer; and wherein the first portion of the gateinsulating layer being situated proximate to the source region andspaced away from the drain region by the second portion of the gateinsulating layer; and wherein the well region having a dopantconcentration less than that of the source region and the drain region,the well region extends at least from source region towards the drainregion so as to completely underlie the first portion of the gateinsulating layer and to underlie at least the second portion of the gateinsulating layer. Preferably, the second thickness is around 30 to 500nm thick (more preferably around 30 to 50 nm thick—and even morepreferably around 34 to 45 nm thick). The first thickness is,preferably, around 10 to 20 nm thick (more preferably around 15 nmthick).

[0006] In an alternative embodiment, the drain region is spaced awayfrom the well region by a second region, and dopants are introduced at afirst concentration into the substrate under the first portion of thegate insulating layer and are introduced into the second region at asecond concentration level which is much less than the firstconcentration level. Preferably, the dopants have a substantially higherconcentration under the first portion of the gate insulating layer thanthe second portion of the gate insulating layer. In another alternativeembodiment, both of the source and drain regions are formed in the wellregion.

[0007] Another embodiment of the instant invention is a transistorformed in a semiconductor substrate of a first conductivity type andhaving an upper surface, the transistor comprising: a well region formedat the upper surface of the semiconductor substrate and having a secondconductivity type opposite that of the first conductivity type; a sourceregion formed at the upper surface of the semiconductor substrate andwithin the well region, the source region formed of the secondconductivity type and spaced from an edge of the well region by a firstportion of the well region, which has a length; a drain region formed ofthe second conductivity type at the upper surface of the semiconductorsubstrates, the drain region spaced from the source region by a channelregion, which has a length, and spaced from the well region by a secondregion, which has a length; a conductive gate structure situated overthe upper surface of the semiconductor substrate and extendingsubstantially the entire length of the channel region, the conductivegate structure having a substantially constant thickness across theconductive gate structure; a gate insulating layer situated between andabutting the upper surface of the semiconductor substrate and theconductive gate structure, the gate insulating layer comprised of: afirst portion of the gate insulating layer which has a first length anda first thickness, the first portion of the gate insulating layersituated over a portion of the channel region and over a portion of thefirst portion of the well region; and a second portion of the gateinsulating layer which as a second length and a second thickness whichis substantially thicker than the first thickness, a portion of thesecond portion of the gate insulating layer situated over the remainderof the first portion of the well region and the remainder of the secondportion of the gate insulating layer situated over the second portion;and wherein the ratio of the length of the first portion of the gateinsulating layer and the length of the second portion of the gateinsulating layer is around 0.4 to 0.6. The length of the channel regionis, preferably, equal to the summation of the length of the firstportion of the well region and the length of the second region.Preferably, the well region has a dopant concentration less than thedopant concentration of the source region or the drain region. Thesecond thickness is, preferably, around 30 to 500 nm thick (morepreferably around 30 to 50 nm thick—and more preferably around 34 to 45nm thick). Preferably, the first thickness is around 10 to 20 nm thick(more preferably around 15 nm thick).

BRIEF DESCRIPTION OF THE DRAWINGS

[0008]FIG. 1a is a cross-sectional view illustrating the devicestructure of one embodiment of the present invention. FIG. 1b is anequivalent circuit diagram of the transistor of FIG. 1a.

[0009]FIGS. 2a and 2 b are graphs illustrating data for the device ofFIG. 1. FIG. 2a is a plot of the ratio of L1/L2 versus R_(sp), V_(T),and BV. FIG. 2b is a graph illustrating V_(gs) versus R_(sp) for variousproportions of thin gate oxide regions (L1) versus thick gate oxideregions (L2).

[0010]FIG. 3 is a cross-sectional view illustrating the device structureof another embodiment of the instant invention.

[0011]FIG. 4 is a graph illustrating dopant concentration versusdistance in the substrate for thin gate dielectric, thick gatedielectric, and split-gate dielectric devices.

[0012]FIGS. 5a, 5 b, and 5 c are graphs illustrating data measured fromthe device of FIG. 3. FIG. 5a is a graph of breakdown voltage versusL1/L2 for various gate lengths (L1+L2). FIG. 5b is a graph of R_(sp)versus L1/L2 for various gate lengths. FIG. 5c is a graph of V_(T)versus L1/L2 for various gate lengths.

[0013] Common reference numerals are used throughout the followingDetailed Description to designate like or equivalent features. Thefigures are not drawn to scale, they are merely provided forillustrative purposes to describe various aspects of the embodiments ofthe instant invention.

DETAILED DESCRIPTION OF THE DRAWINGS

[0014] Basically, the instant invention is a lateral double diffusedmetal oxide semiconductor device (LDMOS) which has a gate structure,comprised of a thin gate dielectric portion (with a length, L1) and athick gate dielectric portion (with a length, L2) situated between thesubstrate (or epitaxial layer situated on a substrate) and theconductive gate electrode. The device of the instant invention will havebeneficial V_(gs) drive performance (provided by the thin gatedielectric portion), yet have good breakdown voltage which is providedby the thicker gate dielectric portions. Device performance(specifically R_(sp)) is improved over traditional thick gate dielectrictransistors where the ratio of L1 to L2 is around 0.4 with standardlogic-type supply voltages (specifically V_(gs) around 5.0 volts).Furthermore, the device of the instant invention has greater breakdownvoltage as compared to standard thin gate dielectric devices.

[0015] The following descriptions of the instant invention will revolvearound the devices of FIGS. 1a and 3. While these descriptions specify acertain dopant type for certain regions, one of ordinary skill in theart knows that the dopant types can be changed so as to go from an NMOSdevice to a PMOS device and vice versa. In addition, while a fabricationmethodology is described below, any fabrication methodology may be used.

[0016] Referring to the embodiment of the instant invention asillustrated in FIGS. 1a and 2 a-2 b, layer 201 may be one layer, whichis the substrate, comprised of single-crystal silicon and region 202would be a deep well region implanted into substrate 201, or layer 201may be comprised of single crystal silicon while layer 202 is comprisedof an epitaxial silicon layer formed on the single-crystal substrate201. If layer 202 is merely a doped region formed in substrate 201, thenit, preferably, is doped with n-type dopants using a conventionalblanket implantation step. However, configuring the device (as isillustrated in FIG. 1a) with layer 201 as the substrate and layer 202 asan epitaxial silicon layer may be easier because the epitaxial layer canbe in-situ doped with n-type dopants as the epitaxial layer is formed.Next, Pwell 204 is formed by masking off a portion of the substrate andimplanting p-type dopants into the substrate. Preferably, Pwell 204 isdoped to around 1×10¹⁷ to 1×10¹⁸ cm⁻³ with boron. An insulating layer isblanketly formed. Preferably, the insulating layer will be comprised ofsilicon dioxide, silicon nitride, an oxynitride stack, a high dielectricconstant material (such as PZT, BST, a silicate, or tantalum pentoxide),or a combination of the above, and it will be around 15 to 30 nm thick(more preferably around 15 to 27.5 nm thick). A patterning layer isformed so that the thicker portion of gate insulator 214 is masked offalong with the rest of the wafer except for the portion where thethinner portion of gate insulator 214 will be formed. Once theseportions are masked off, a low-voltage V_(T) implant is performed toform implant region 220. Preferably, the implant is accomplished usingboron with a dosage around 5×10¹¹ to 5×10¹² cm⁻³ and an energy around 20keV. The resulting dosage of implant region 220 is preferably on theorder of 1×10¹⁷ to 5×10¹⁷ cm⁻³. As is shown in FIG. 1a, dopants 220,preferably, have a higher concentration under the thin gate dielectricportion and have a much lower concentration (maybe near substantially noimplanted V_(T) adjust dopants as you move from the thin dielectricportion to the thicker dielectric portion). This is illustrated in FIG.4 which basically shows the V_(T) adjust implant for a device with onlya thin dielectric, only a thick dielectric, and the device of theinstant invention.

[0017] The portion of the dielectric layer which is situated in theregion where the thinner portion of gate dielectric 214 is to be formedis removed, the portion above where the thicker portion of gatedielectric 214 is to be formed is to remain in place, and the remainderof the dielectric layer may or may not be removed. This may beaccomplished using a standard deglaze step or any other conventionaldielectric removal step. After the removal step, all of the maskinglayer is removed and another dielectric formation step is performed.This dielectric layer is preferably comprised of the same material andis formed in the same fashion as the prior dielectric layer (preferablya thermally grown silicon dioxide layer). This dielectric layer ispreferably on the order of 10 to 20 nm thick (more preferably around 15nm thick). The result of this formation step will be a thin dielectricportion with a length, L1, and a thick dielectric portion with a length,L2. The thin dielectric portion will preferably have a thickness ofaround 10 to 20 nm (more preferably around 15 nm) and the thickerportions will have a thickness around 30 to 45 nm (more preferablyaround 30 to 42.5 nm).

[0018] The gate electrode 218 is formed by blanketly forming a layer ofpolycrystalline silicon (either doped in-situ or doped in a laterimplantation step) or other conductor (such as tungsten, tungstennitride, tantalum, tantalum nitride, aluminum, titanium, or titaniumnitride), and then patterning and etching away the excess material so asto form conductive gate structure 218. Using conventional implantationtechniques, lightly doped drain (LDD) regions 211 and 212 are formedusing an implant of ions at a dosage of around 1×10¹³ to 1×10¹⁴ cm⁻³with an implantation energy of around 20 to 80 keV. In this embodimentof the instant invention (i.e. an n-type LDMOS device), the dopant isphosphorous, however, for a p-type device the dopant would be comprisedof boron.

[0019] Sidewall insulators 216 are formed using conventional techniques.Next, source region 208 and drain region 210 are formed using thesidewall spacers for alignment. Since the device depicted in FIG. 1 isan n-type device, for example, source region 208 and drain region 210are doped with n+ dopants (p+ type dopants would be used for a p-typedevice). Preferably, source region 208 and drain region 210 are dopedwith arsenic or phosphorous at a dosage around 1×10¹⁵ to 5×10¹⁵ cm⁻³with an implant energy around 50 to 150 keV. Like other implantedregions, the dopants diffuse to some extent to form graded junctions andto diffuse the source region 208 and drain region 210 at least partiallyunder conductive gate structure 218 during subsequent higher temperaturesteps (for example, thermal steps which are in excess of around 700 to1150 C.). Doped region 206 is preferably doped with a dopant typeopposite that of source region 208 if it is formed at all. Preferably,doped region 206 is doped with boron at a dosage around 1×10¹⁵ to 5×10¹⁵with an implant energy around 10 to 30. Doped region 206 is beneficialbecause it provides a connection from the backgate to the source so asto reduce the parasitic bipolar affect formed by a parasitic NPNtransistor from between regions 208, 204, 210, respectively. It isimportant to situate region 206 as close to source region 208 so as toreduce the amount of resistance between region 204 and 206.

[0020] An important feature of this embodiment of the instant inventionis that Pwell 204 extends completely under the portion of the gatestructure overlying the thin portion of the gate dielectric and extendspartially under the gate structure overlying the thicker gatedielectric. However, Pwell 204 does not extend to drain region 210 oreven to LDD region 211. This is important because an acceptably highbreakdown voltage. In addition, the V_(T) implant situated under theportion of the gate electrode which overlies the thin gate dielectrichas a higher concentration than does the other portions of the implant.This is important to have an acceptably low threshold voltage.

[0021] An equivalent circuit diagram of the device of FIG. 1a isillustrated in FIG. 1b. Device 10 illustrates the thick gate dielectricportion of the device and device 12 illustrates the thin gate dielectricportion of the device. Variable resistance 14 is shown between device 10and drain 210. The resistance of variable resistance 14 depends on thedoping of LDD 211, drain region 210, well region 204, dopant region 220and region 202. The portion of the channel of the device looks like ithas a length of (L1+L2). However, due to the doping levels of the device(more specifically, dopants 220), the effective channel is given, prettymuch, by L3.

[0022]FIGS. 2a and 2 b illustrate advantages of the split gatedielectric of the instant invention. FIG. 2a is a graph of R_(sp),V_(T), and breakdown voltage versus the ratio of L1/L2. As can be seenby this graph, for ratios of L1/L2 between around 0.3 to 0.6 (morepreferably around 0.4 to 0.6) the threshold voltage, V_(T), and thevalue of R_(sp) decrease while the breakdown voltage remains fairlyhigh. This is desired. Optimally, the device of the instant inventionwould have minimum values for R_(sp) and V_(T) while having a fairlyhigh breakdown voltage. The lower values of R_(sp) and V_(T) (ascompared to a device which only has a thick gate dielectric) areobtained from the thin gate dielectric portion and the tailoring of theV_(T) implant such that the concentration of the implant is greater(preferably around 1×10¹⁷ cm⁻³) under the thin gate dielectric portionand lower (preferably around 1×10¹⁶ cm⁻³) under the thick gatedielectric portion. The greater breakdown voltages (as compared to adevice which only has a thin gate dielectric portion) is achieved fromhaving a specific proportion of the gate structure having a thicker gatedielectric.

[0023]FIG. 2b is a graph of R_(sp) versus V_(gs) for various values ofL1/L2. This graph illustrates that for values of L1/L2 that are greaterthan around 0.4, the value of R_(sp) remains relatively constant fordiffering values of V_(gs).

[0024]FIG. 4 is a graph illustrated simulated doping profiles along thechannel for a thin-gate dielectric LDMOS device, a thick-gate LDMOSdevice and the LDMOS device of the instant invention. The difference inthe concentration for the thin-gate and thick gate devices is the lowvoltage V_(T) adjust implant.

[0025] Basically, the transistor of this embodiment of the instantinvention (as illustrated in FIGS. 1a and 1 c) has the thin gate oxidecompletely situated over the MOS inversion channel. Whereas only part ofthe thick gate oxide is situated over the MOS inversion channel. Inessence the transistor of the instant invention is a true step gateoxide with the change in gate oxide thick occuring directly over thechannel (whose length is given as L3) over the transistor.

[0026] Referring to the embodiment of FIG. 3, MOS device 300 utilizesthe same gate structure of the instant invention as that LDMOS device ofFIG. 1. Like the device of FIG. 1, the following description of device300 is provided assuming that the device is an n-type device. However,device 300 may be an n-type device or a p-type device. One of ordinaryskill in the art would know on the teachings of this application how toconvert the n-type device into a p-type device. As was stated above,device 300 utilizes the gate structure of the instant invention whereina portion of the gate dielectric is thin (preferably around 10 to 20 nmthick—more preferably around 15 nm thick) and has a length, L1, andanother portion is thick (preferably around 30 to 45 nm thick—morepreferably around 34 to 40 nm thick) and has a length, L2.

[0027] Preferably, if device 300 is an NMOS device, substrate 202 isdoped to be of either n-type or p-type and epitaxial layer 304 is formedto be a p type well. Source region 208 and drain region 210 are,preferably, implanted with n-type (such as phosphorous or arsenic) at animplant energy of around 50 to 150 keV with a dopant dosage around1×10¹⁵ to 5×10¹⁵ cm⁻³. LDD regions 212 and 211 are preferably formedfrom n-type dopants and are preferably more lightly doped than sourceregion 208 and drain region 210. The threshold voltage implant 220 has,preferably, a greater concentration (preferably around 1×10¹⁷ to 5×10¹⁷cm⁻³) of dopants under the thin gate dielectric portion and a lower(preferably around 1×10¹⁶ to 5×10¹⁶ cm⁻³), may be even graded,concentration of dopants under the thick gate dielectric portion.

[0028] Just like the LDMOS structure of the instant invention, the MOSstructure of the instant is advantageous because it provides the powerperformance (i.e. higher breakdown voltages) of a power device whilestill having the performance of the faster and lower power logic devices(i.e. lower R_(sp) and lower threshold voltage).

[0029]FIGS. 5a, 5 b, and 5 c are graphs of measured data comparing thelength of the thin gate dielectric portion (L1) versus breakdownvoltage, R_(sp) and V_(T), respectively. The graphs are provided forthree different total gate lengths. More specifically, with a gatelength of 0.72 microns, 0.9 microns, and 1.08 microns.

[0030] Although specific embodiments of the present invention are hereindescribed, they are not to be construed as limiting the scope of theinvention. Many embodiments of the present invention will becomeapparent to those skilled in the art in light of methodology of thespecification. The scope of the invention is limited only by the claimsappended.

What we claim is:
 1. A transistor formed on a semiconductor substrate ofa first conductivity type and having an upper surface, said transistorcomprising: a well region formed in said semiconductor substrate, saidwell region of a second conductivity type opposite that of the firstconductivity type; a source region formed in said well region in saidsemiconductor substrate, said source region of said second conductivitytype; a drain region formed in said semiconductor substrate and spacedaway from said source region by a channel region, said drain region ofsaid second conductivity type; a conductive gate electrode disposed oversaid semiconductor substrate and over said channel region; a gateinsulating layer disposed between said conductive gate electrode andsaid semiconductor substrate and having a length, said gate insulatinglayer comprising: a first portion of said gate insulating layer whichhas a first length and a first thickness; a second portion of said gateinsulating layer which has a second length and a second thickness whichis substantially thicker than said first thickness, the sum of saidfirst length and said second length equalling the length of said gateinsulating layer; and wherein said first portion of said gate insulatinglayer being situated proximate to said source region and spaced awayfrom said drain region by said second portion of said gate insulatinglayer; and wherein said well region having a dopant concentration lessthan that of the source region and the drain region, said well regionextends at least from source region towards said drain region so as tocompletely underlie said first portion of said gate insulating layer andto underlie at least said second portion of said gate insulating layer.2. The transistor of claim 1, wherein said second thickness is around 30to 500 nm thick.
 3. The transistor of claim 1, wherein said secondthickness is around 30 to 50 nm thick.
 4. The transistor of claim 1,wherein said second thickness is around 34 to 45 nm thick.
 5. Thetransistor of claim 1, wherein said first thickness is around 10 to 20nm thick.
 6. The transistor of claim 1, wherein said first thickness isaround 15 nm thick.
 7. The transistor of claim 1, wherein said drainregion is spaced away from said well region by a second region.
 8. Themethod of claim 7, wherein dopants are introduced at a firstconcentration into said substrate under said first portion of said gateinsulating layer and are introduced into said second region at a secondconcentration level which is much less than said first concentrationlevel.
 9. The method of claim 8, wherein said dopants have asubstantially higher concentration under said first portion of said gateinsulating layer than said second portion of said gate insulating layer.10. The transistor of claim 1, wherein both of said source and drainregions are formed in said well region.
 11. A transistor formed in asemiconductor substrate of a first conductivity type and having an uppersurface, said transistor comprising: a well region formed at said uppersurface of said semiconductor substrate and having a second conductivitytype opposite that of said first conductivity type; a source regionformed at said upper surface of said semiconductor substrate and withinsaid well region, said source region formed of said second conductivitytype and spaced from an edge of said well region by a first portion ofsaid well region, which has a length; a drain region formed of saidsecond conductivity type at said upper surface of said semiconductorsubstrates, said drain region spaced from said source region by achannel region, which has a length, and spaced from said well region bya second region, which has a length; a conductive gate structuresituated over said upper surface of said semiconductor substrate andextending substantially the entire length of said channel region, saidconductive gate structure having a substantially constant thicknessacross the conductive gate structure; a gate insulating layer situatedbetween and abutting said upper surface of said semiconductor substrateand said conductive gate structure, said gate insulating layer comprisedof: a first portion of said gate insulating layer which has a firstlength and a first thickness, said first portion of said gate insulatinglayer situated over a portion of said channel region and over a portionof said first portion of said well region; and a second portion of saidgate insulating layer which as a second length and a second thicknesswhich is substantially thicker than said first thickness, a portion ofsaid second portion of said gate insulating layer situated over theremainder of said first portion of said well region and the remainder ofsaid second portion of said gate insulating layer situated over saidsecond portion; and wherein the ratio of said length of said firstportion of said gate insulating layer and said length of said secondportion of said gate insulating layer is around 0.4 to 0.6.
 12. Themethod of claim 11, wherein the length of said channel region is equalto the summation of the length of said first portion of said well regionand the length of said second region.
 13. The transistor of claim 11,wherein said well region has a dopant concentration less than the dopantconcentration of said source region or said drain region.
 14. Thetransistor of claim 11, wherein said second thickness is around 30 to500 nm thick.
 15. The transistor of claim 11, wherein said secondthickness is around 30 to 50 nm thick.
 16. The transistor of claim 11,wherein said second thickness is around 34 to 45 nm thick.
 17. Thetransistor of claim 11, wherein said first thickness is around 10 to 20nm thick.
 18. The transistor of claim 11, wherein said first thicknessis around 15 nm thick.